FIELD OF THE INVENTION
The invention relates to an integrated electrical circuit having at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters which are electrically connected to one another, the inverters each contain two complementary MOS transistors having a source, a drain and a channel, and the channels of the complementary MOS transistors have different conductivity types.
A static semiconductor memory cell of this type is preferably configured as a bistable flip-flop. The flip-flop has two stable states. Memory cells of this type are distinguished by their short access time, which is of the order of magnitude of a few ns.
Furthermore, the memory cell can be integrated into a CMOS basic process by which the integrated electrical circuit is fabricated. In order to enable random access, the memory cell also contains two bit lines and a word line in addition to the two terminals necessary for the application of an electrical potential. A memory cell of this type is referred to as static random access memory (SRAM).
The static memory cell can be realized in the CMOS basic process without additional process steps. Therefore, it can also be integrated into complex logic circuits such as microprocessors. However, it is likewise possible to construct a memory cell configuration with memory cells of this type. It is also possible to replace DRAMs with SRAMs of this type, and this is advantageous owing to the shorter access time and also owing to the lower activation power.
One disadvantage of SRAMs is the large area that they occupy. Given a minimum feature size F, the memory typically taken up per memory cell is 8 F.sup.2 in the case of DRAMs, 60 F.sup.2 in the case of SRAMs with a 6-transistor cell or 45 F.sup.2 in the case of SRAMs with a cell formed from four transistors and, in addition, two thin film transistors (TFT). A TFT is a MOS transistor with a channel region made of polycrystalline silicon that can be disposed above other transistors.
The minimum feature size F is preferably of the order of magnitude of 0.1 um to 0.5 um, values of 0.18 um to 0.35 um being preferred. However, it is foreseeable that this feature size will be able to be reduced further by a further development of the process technology, in particular of the photolithographic methods used.
Arranging TFTs above other transistors results in vertical integration, which reduces the area requirement. However, an area requirement of 45 F.sup.2 remains considerably larger than the area occupation of 8 F.sup.2 in the case of DRAMs. A solution to this disadvantage has not been disclosed to date.